Analysis on Optimal Chip Floorplanning Considering Various Types of Decoupling Capacitors in Package PDN

Abstract

In this paper, to improve PI (Power Integrity) performance of system-level PDN (Power Delivery Network), the optimal arrangement of various package decoupling capacitors and on-chip IPs (Intellectual Property) are analyzed from the co-design point of view. By applying decoupling capacitor to the package PDN, impedance peak of the system-level PDN can be lowered in the frequency domain, and so does the voltage drop in the time domain. In this paper, the PI performance improvement effect according to the location of the package decoupling capacitor is analyzed. Furthermore, it is confirmed that the inductance generated in the package PDN should be reduced to optimize the PI improvement effect of the package decoupling capacitor. A method to reduce the inductance of such package PDN, especially bump-to-decap inductance, is analyzed from the co-design point of view of on-chip PDN and package PDN. Therefore, in this paper, it is proposed what should be considered in the chip floorplanning stage for optimization of PDN from IP to DSC, especially for the case where DSC is applied.