Improving of Dynamic IRdrop Performance in FinFET SoC Design

Abstract

In this paper, we have improved dynamic IRdrop performance in large SoC design through various dynamic IRdrop reduction technique. Robust power/ground rail structure is proposed and applied to standard cell power/ground pin connection. Manual adding extra power switch cell is applied to fix localized IRdrop hot-spot. For memory macro, sharing power/ground metal scheme is shown significant improvement memory IRdrop performance. Those techniques are fully adopted in our FinFET based SoC implementation stage. As a result makes it easier to sign-off full-chip IRdrop compared to traditional physical design methodology.