Accurate, scalable and informative design space exploration for large and sophisticated multi-core oriented architectures

Chang-Burm Cho, James Poe, Tao Li, Jingling Yuan
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引用次数: 2

Abstract

As microprocessors become more complex, early design space exploration plays an essential role in reducing the time to market and post-silicon surprises. The trend toward multi-/many- core processors will result in sophisticated large-scale architecture substrates (e.g. non-uniformly accessed caches interconnected by network-on-chip) that exhibit increasingly complex and heterogeneous behavior. While conventional analytical modeling techniques can be used to efficiently explore the characteristics (e.g. IPC and power) of monolithic architecture design, existing methods lack the ability to accurately and informatively forecast the complex behavior of large and distributed architecture substrates across the design space. This limitation will only be exacerbated with the rapidly increased integration scale (e.g. number of cores per chip). In this paper, we propose novel, multi-scale 2D predictive models which can efficiently reason the characteristics of large and sophisticated multi-core oriented architectures during the design space exploration stage without using detailed cycle-level simulations. Our proposed techniques employ 2D wavelet multiresolution analysis and neural network regression modeling. We extensively evaluate the efficiency of our predictive models in forecasting the complex and heterogeneous characteristics of large and distributed shared cache interconnected by a network on chip in multi-core designs using both multi-programmed and multithreaded workloads. Experimental results show that the models achieve high accuracy while maintaining low complexity and computation overhead. Through case studies, we demonstrate that the proposed techniques can be used to informatively explore and accurately evaluate global, cooperative multi-core resource allocation and thermal-aware designs that cannot be achieved using conventional design exploration methods.
准确的,可扩展的和信息丰富的设计空间探索大型和复杂的多核面向架构
随着微处理器变得越来越复杂,早期的设计空间探索在减少上市时间和后硅惊喜方面起着至关重要的作用。多核/多核处理器的趋势将导致复杂的大规模架构基板(例如,通过片上网络相互连接的非均匀访问缓存)表现出越来越复杂和异构的行为。虽然传统的分析建模技术可以用来有效地探索单片架构设计的特征(例如IPC和功率),但现有的方法缺乏准确和信息地预测整个设计空间中大型分布式架构基板的复杂行为的能力。这种限制只会随着集成规模的迅速增加而加剧(例如,每个芯片的核心数量)。在本文中,我们提出了新颖的多尺度二维预测模型,该模型可以在设计空间探索阶段有效地推断大型复杂的多核面向架构的特征,而无需使用详细的循环级模拟。我们提出的技术采用二维小波多分辨率分析和神经网络回归建模。我们广泛评估了我们的预测模型在预测大型和分布式共享缓存的复杂和异构特性方面的效率,这些缓存是由多核设计中使用多编程和多线程工作负载的片上网络连接的。实验结果表明,该模型在保持较低的复杂度和计算开销的同时,获得了较高的精度。通过案例研究,我们证明了所提出的技术可以用于信息探索和准确评估全局,协作多核资源分配和热感知设计,这是传统设计勘探方法无法实现的。
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