Differential Scoring for Systolic Sequence Alignment

A. E. D. L. Serna
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引用次数: 2

Abstract

Systolic implementations of dynamic programming solutions that utilize a similarity matrix can achieve appreciable performance with both course-and fine-grain parallelization. A limitation of systolic array design is that score routing between array elements, array I/O bandwidth, and score memory capacity are dependent upon the length of the sequence that can be processed. A novel approach of differential scoring is presented that exploits adjacency and decouples the complexity of score routing and systolic array bandwidth to sequence length. Instead, these design parameters become a function of algorithm sensitivity. As a consequence, the Simile implementation of differential scoring for sequence alignment has reduced score routing, I/O bandwidth, and score storage by 82% for sequences of length 10 and has significantly improved gate count, clock rate, and power utilization per systolic processing element.
收缩序列比对的差异评分
利用相似矩阵的动态规划解决方案的收缩实现可以在粗粒度和细粒度并行化中获得可观的性能。收缩阵列设计的一个限制是阵列元素之间的分数路由、阵列I/O带宽和分数内存容量取决于可以处理的序列的长度。提出了一种新的差分评分方法,利用邻接性,将评分路由的复杂性和收缩阵列带宽与序列长度解耦。相反,这些设计参数变成了算法灵敏度的函数。因此,对于长度为10的序列,用于序列对齐的差分评分的明码实现减少了82%的分数路由、I/O带宽和分数存储,并显著提高了门计数、时钟速率和每个收缩处理元素的功率利用率。
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