A Low Complexity Timing Synchronization Algorithm for DTMB Standard

Abstract

In this paper, a novel timing synchronization method based on phase rotation PN Frame Header for DTMB standard is presented. The combined one sample per chip hard-limiting digital matched filters (HL-DMF) and serial correlators are applied to the timing recovery algorithm. Multiple-dwell PN code detection engine is used, which gives much more accurate timing recovery in terms of lower false detection probability and lower probability of missing the synchronization signal. The hardware resource is substantially reduced, and more conducive to implementation and ASIC design. Simulation and hardware test show that both in the presence of Gaussian noise and in multipath fading channels, the performance is very good when using this method, particularly in the situation of the low SNR.