A dual-mode DC/DC converter for ultra-low-voltage microcontrollers

J. De Vos, D. Flandre, D. Bol
{"title":"A dual-mode DC/DC converter for ultra-low-voltage microcontrollers","authors":"J. De Vos, D. Flandre, D. Bol","doi":"10.1109/SUBVT.2012.6404306","DOIUrl":null,"url":null,"abstract":"Ultra-low-voltage processors of highly duty-cycled applications such as wireless sensor nodes must support two modes of operation: active mode and sleep mode. Even in sleep mode some critical blocks such as retentive SRAM, timer and interrupt controller must remain powered-on. The DC/DC converter thus need to be able to supply ultra-low loads corresponding to sleep mode. In this paper, we propose a dual-mode switched-capacitor DC/DC converter to power such ultra-low-voltage processors with high efficiencies in both modes. It delivers a 0.3-0.4V output voltage from a 1-1.2V input source. The 0.12mm2 chip was manufactured in a 0.13μm CMOS technology. The efficiency reaches 74% with a 100 μW load and 63% with a 100nW load, corresponding to the processor active and sleep mode respectively. Adaptive body biasing and adaptive internal clock generation supplied by the output voltage allow the converter to correctly operate over a wide load range from 25nW to 125 μW, i.e. nearly 4 orders of magnitude.","PeriodicalId":383826,"journal":{"name":"2012 IEEE Subthreshold Microelectronics Conference (SubVT)","volume":"395 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE Subthreshold Microelectronics Conference (SubVT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SUBVT.2012.6404306","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10

Abstract

Ultra-low-voltage processors of highly duty-cycled applications such as wireless sensor nodes must support two modes of operation: active mode and sleep mode. Even in sleep mode some critical blocks such as retentive SRAM, timer and interrupt controller must remain powered-on. The DC/DC converter thus need to be able to supply ultra-low loads corresponding to sleep mode. In this paper, we propose a dual-mode switched-capacitor DC/DC converter to power such ultra-low-voltage processors with high efficiencies in both modes. It delivers a 0.3-0.4V output voltage from a 1-1.2V input source. The 0.12mm2 chip was manufactured in a 0.13μm CMOS technology. The efficiency reaches 74% with a 100 μW load and 63% with a 100nW load, corresponding to the processor active and sleep mode respectively. Adaptive body biasing and adaptive internal clock generation supplied by the output voltage allow the converter to correctly operate over a wide load range from 25nW to 125 μW, i.e. nearly 4 orders of magnitude.
一种用于超低电压微控制器的双模DC/DC转换器
高占空比应用(如无线传感器节点)的超低电压处理器必须支持两种工作模式:活动模式和睡眠模式。即使在睡眠模式下,一些关键的块,如保留SRAM,定时器和中断控制器必须保持通电状态。因此,DC/DC转换器需要能够提供与休眠模式相对应的超低负载。在本文中,我们提出了一种双模开关电容DC/DC转换器,为这种超低电压处理器供电,在两种模式下都具有高效率。它从1-1.2V输入源提供0.3-0.4V输出电压。该0.12mm2芯片采用0.13μm CMOS工艺制造。负载为100 μW时效率达到74%,负载为100nW时效率达到63%,分别对应于处理器的活动模式和休眠模式。由输出电压提供的自适应体偏置和自适应内部时钟产生使变换器能够在25nW至125 μW的宽负载范围内正确工作,即近4个数量级。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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