Multi-level approaches to low power 16-bit ALU design

Abstract

A low power 16-b ALU has been designed at the transistor level. The designed ALU performs 16 instructions and has a two-stage pipelined architecture. For low power consumption we propose a new ALU architecture which has efficient propagation (P) and generation (G) block schemes of ELM adder. The adder of the proposed ALU is disabled while the logic operation is performed and vice versa. Outputs of each P block are separated to the dual output bus to reduce switching capacitance during the ALU operation. The proposed ALU was simulated with O.6/spl mu/m single-poly triple-metal CMOS process. As a result of post-layout simulations, addition time of the core is about 5ns with 3. 3 V supply voltage and the average power consumption of the core was 54 mW at 200 MHz.