Design of Area-Power-Delay Efficient Square Root Carry Select Adder

Abstract

This work proposes a simple and efficient way of designing a Square-root Carry Select Adder (SQRT-CSLA). The transistor-level modification in the Carry Select Adder (CSLA) significantly reduces the hardware complexity and power dissipation. Based on this modification, an 8-bit, 16-bit, 32-bit and 64-bit Square-root CSLA architecture is designed. The proposed design is simulated at a transistor level in a 180 nm, CMOS technology with a supply voltage of 1.8 V. The proposed design is able to achieve 30% reduction in Power-Delay Product (PDP) compared to the existing architectures.