The Implementation of High Speed Parallel Timing Synchronization Algorithm Based on FPGA

Abstract

In this paper, a high speed parallel timing synchronization algorithm is proposed and implemented on the hardware platform, which includes the linear interpolation module, the timing error detection module based on Gardner algorithm, the numerically controlled oscillator module based on the binary operation rule and the loop filter module, a timing adjustment module is also employed. Unlike the conventional serial timing synchronization algorithm, they are all parallel implementation. Meanwhile, the simulation shows that this algorithm is not only easy to implement, but also consumes little hardware resources and performs very well. Thus, it can be widely used in high-speed parallel digital receiver system.