Design and implementation of a SHARC digital signal processor core in Verilog HDL

Abstract

This work describes the design and implementation of an 8-bit fixed point digital signal processor core in Verilog HDL. The architecture exploits the principles of pipelining and parallelism in order to obtain high speed and throughput. The modules of the design fit on a Xilinx XC4010XL FPGA with 130 K gates running at a clock frequency of 32.31 MHz. The proposed architecture follows the Analog Devices SHARC/sup /spl reg// (super Harvard architecture) DSP standard. This DSP architecture balances a high performance processor core with high performance buses, program memory (PM) and data memory (DM). In the core, every instruction can execute in a single cycle. The buses and instruction cache provide rapid, unimpeded dataflow to the core to maintain the execution rate.