Implementation of CPA analysis against AES design on FPGA

Abstract

Physical implementations of cryptographic algorithms may let relatively side channel information. By analyzing this information leakage, the confidential data, like the cryptographic keys, can be revealed. The correlation power analysis(CPA) is a well-known attack of the cryptographic device. This paper conduces a successful CPA of the Advanced Encryption Standard AES implemented on the Xilinx FPGA with the Side-channel Attack Standard Evaluation Board (SASEBO). The experimental results show that the choice of the power model and the number of power traces can further improve the performance of CPA attack in extracting the correct key.