Pre-layout noise suppression and delay estimation with decap allocation for 1-k point FFT core

Abstract

This paper addresses the decoupling capacitance estimation and allocation based on noise suppression at the prelayout level. Power supply noise (PSN) is an important issue among all the issues in today's application Specific Integrated Circuits (ASIC) design. Present trends in VLSI design are inclined towards the placement of decoupling capacitors for multi-core design. An early prediction and estimation of decoupling capacitance in the pre-layout stage of the design can provide a better scope in optimizing power, noise and delay effects for the circuit. In this paper, we investigate the change in noise and delay parameters with and without the decap allocation for multi-core circuit at the pre-layout stage. Here a 1024 point FFT core is considered as an example for our test circuits as they are quite complex in nature and are also used as custom cores in many applications. To the best of our knowledge PDN analysis for execution time and noise suppression on FFT application cores is not available in related research works. The novelty of our work lies in the fact that by using our approaches noise can be suppressed approximately by 37% on an average at the prelayout stage and 1.84% increase in increase in propagation delay when compared to the original circuitry. This early prediction of CAD implementation helps to create more accurate designs at the layout stage and hence this work can serve as benchmarks for PDN analysis.