Testability analysis of CMOS ternary circuits

Abstract

The testability of ternary CMOS gates was examined in order to find suitable test vectors to detect stuck-at, stuck-open, and stuck-short faults. A two-level fault model approach was used: a transistor-by-transistor model for low component count operators and a gate-level model for large component count operators. Results are given in a tabular format for each gate. Since these ternary CMOS circuits operate on the set (0,1,2) compared to similar CMOS binary circuits which operate on the set