The Relationship between Packaging Structures, Chip Area and Thermal Resistance of NMOS Semiconductor in Transient Dual Interface Method

Abstract

This paper summarizes the relationship between packaging structures, chip area and junction-to-case thermal resistance (Rthjc) of XX NMOS semiconductor in transient dual interface (TDI) method: (1)The Rthjc of this NMOS transistor is determined to be 0.48K/W directly from the separation of transient thermal resistance Zth curves. The influence of each packaging structure on Rthjc is then analyzed with cumulative and differential structure functions. The Rthjc mainly contains thermal resistance of PN junction, Sn-based solders, BeO ceramic and metal case. The thermal resistance of this NMOS is relatively small compared with that of other NMOS devices. (2)Chip area A can be calculated with heating power, chip thermal parameters and slope of transient initial junction temperature curves. The larger the slope of initial junction temperature curves, the smaller the chip area A. (3)With the same packaging structures, the smaller the chip area A, the larger the thermal resistance Rthjc.