Advanced Extensible Crossbar Protocol for Connecting Multi-Cores and Shared-Memory on-Chip

Abstract

With the development of the chip industry, the bandwidth of interconnect on-chip are becoming more and more important for the performance of chip system. However, heterogeneous Intelligent Property (IPs) including cores and memory banks are being integrated in one chip which makes the hardware design of interconnect difficult. In this paper, we present Advanced Extensible Crossbar (AEC) protocol used for describing and designing the bus on-chip. It can support most of features in Advanced eXtensible Interface (AXI) protocol. Our AEC-based crossbar has been implemented with connecting 8 processors (the area of each one is 13.2 mm2) and 16 MB Static Random Access Memory (SRAM, the area is 1.87 mm2/MB) in TSMC 28nm HPC process and the results show that it can achieve high frequency of 800 MHz after place and route (P&R) while the area requirement is 0.065 mm2. Compared with AXI-based crossbar provided by Synopsys, our AEC-based crossbar gives 1.45X frequency increase and 8X area requirement saving.