Design and Analysis of 4*4-Bit Vedic Multiplier with 32nm CNFET Technology

Abstract

Carbon Nanotubes Field Effect Transistors (CNFETs) have shown numerous advantages over conventional Metal Oxide Semiconductor FETs (MOSFETs) and CMOS in terms of decreased short channel effect, lower power consumption and high performance. As the transistor channel length shortens to below 10 nm in length, short channel effects, such as drain-induced barrier lowering and velocity saturation, becomes prominent, which negatively impact transistor performance and reliability. As CNFETs do not show scaling issues, CNFETs based digital circuit designs, such as adder and multiplier, can possibly show better results in terms of power consumption and propagation delay. Multiplication operation is a crucial operation whose application ranges from computing convolution to fast fourier transform. Hence, it is important to have an efficient architecture and high-performance multiplier. Array multipliers, Wallace and Booth’s multipliers are some of the existing multipliers. One approach to perform high-performance multiplication is through the Vedic Multiplier, whose algorithm reduces delay and power consumption. Many of the pre-existing Vedic multipliers implementations techniques such as MUX based adder, Carry select adder, Hybrid 13T Full Adder rely on CMOS technology for their implementation which brings the challenges like short channel effect while scaling of CMOS transistors. Because CNFETs do not show scaling issues the performance of Vedic multiplier can be improved using CNFETs. This paper proposes a 4*4-bit Vedic Multiplier using 32nm CNFET Technology. The proposed implementation is simulated using HSPICE simulation tool, CosmosScope (cscope) software and Stanford CNFET Model file. The delay and power consumption parameters are measured for various supply voltages. Moreover, the comparative analysis of the aforementioned parameters has also been done by changing the chirality of the transistors.