Instruction and data cache peak temperature reduction using cache access balancing in embedded processors

Abstract

In this work we study cache peak temperature variation under different cache access patterns. In particular we show that unbalanced cache access results in higher cache peak temperature. This is the result of frequent accesses made to overused cache sets. Moreover we study cache peak temperature under cache access balancing techniques and show that exploiting such techniques not only reduces cache miss rate but also results in lower peak temperature. Our study shows that balancing cache access reduces peak temperature by up to 20% and 12% for instruction and data caches respectively. This temperature reduction reduces peak temperature in neighbor components by up to 7%.