Comparisons and analysis of massively parallel SIMD architectures for parallel logic simulation

Eunmi Choi, M. Chung, Yunmo Chung
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Abstract

This paper compares and analyzes massively parallel SIMD architectures as processing environments for parallel logic simulation. The CM-2 and the MP-1 are considered as target machines for the comparison. Detailed contrasts between the two parallel schemes are made based on actual simulation results and system performance. Distributed event-driven simulation protocols are used to obtain experimental results for the two massively SIMD machines. According to the results, the MP-1 is 2 to 2.5 times faster than the CM-2 for up to 16 K gate benchmark circuits, while the CM-2 can accommodate circuits with a larger number of gates of processors. The presented comparisons and analysis of the two machines can be used to choose a SIMD machine for efficient parallel logic simulation.
用于并行逻辑仿真的大规模并行SIMD体系结构的比较与分析
本文比较分析了大规模并行SIMD体系结构作为并行逻辑仿真的处理环境。CM-2和MP-1被认为是比较的目标机。根据实际仿真结果和系统性能对两种并行方案进行了详细对比。采用分布式事件驱动仿真协议对两台大型SIMD机器进行了实验验证。根据结果,MP-1的速度是CM-2的2到2.5倍,适用于16k门基准电路,而CM-2可以适应具有更多处理器门数的电路。通过对两种机器的比较和分析,可以为选择一种SIMD机器进行高效的并行逻辑仿真提供参考。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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