A reconfigurable real-time RISC computer system

D.P. Gluch, B. Furht, G. Coville, J. Green, G. Heikkinen, C. Raeuber, G. Spicker, A. Alberto, S. Correll, S. Geffin, M. Guerrero, B. Routt, W. Sitterberg
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引用次数: 0

Abstract

The hardware architecture of a modular redundant and reconfigurable RISC- (reduced-instruction-set-computer) based fault-tolerant computer system that meets the high availability requirements of real-time applications is presented. A range of redundancy levels is available, and these levels can be defined by the user during the initial or any subsequent system configuration process. Fail-operational capabilities are provided for processor, memory, internal bus, I/O, and power source subsystem failures, and an optional uninterruptible power supply is available. The system protects both stored and output data from corruption upon failures, and the system's fault tolerance and redundancy are transparent to the user. Overall, the fault-tolerance functions are closely integrated with diagnostic software to facilitate system maintenance and repair.<>
一个可重构的实时RISC计算机系统
提出了一种基于模块化冗余可重构精简指令集计算机的容错计算机系统的硬件结构,以满足实时应用的高可用性要求。有一系列可用的冗余级别,这些级别可以由用户在初始或任何后续系统配置过程中定义。为处理器、内存、内部总线、I/O和电源子系统故障提供故障操作功能,并提供可选的不间断电源。系统保护存储和输出数据在故障时不受损坏,系统的容错和冗余对用户是透明的。总体而言,容错功能与诊断软件紧密结合,便于系统维护和维修。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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