H. Akatsu, R. Weis, K. Cheng, M. Seitz, M. Kim, R. Ramachandran, T. Dyer, B. Kim, D. Kim, R. Malik, J. Strane, T. Goebel, O. Kwon, C. Sung, P. Parkinson, K. Wilson, I. McStay, M. Chudzik, D. Dobuzinsky, M. Jacunski, C. Ransom, K. Settlemyer, L. Economikos, A. Simpson, A. Knorr, M. Naeem, G. Stojakovic, W. Robl, O. Gluschenkov, B. Liegl, C. Wu, Q. Wu, W.-K. Li, C.J. Choi, N. Arnold, T. Joseph, K. Varn, M. Weybright, K. McStay, W. Kang, Y. Li, S. Bukofsky, R. Jammy, R. Schutz, A. Gutmann, W. Bergner, R. Divakaruni, D. Back, E. Crabbé, W. Müller, G. Bronner
{"title":"A highly manufacturable 110 nm DRAM technology with 8F/sup 2/ vertical transistor cell for 1Gb and beyond","authors":"H. Akatsu, R. Weis, K. Cheng, M. Seitz, M. Kim, R. Ramachandran, T. Dyer, B. Kim, D. Kim, R. Malik, J. Strane, T. Goebel, O. Kwon, C. Sung, P. Parkinson, K. Wilson, I. McStay, M. Chudzik, D. Dobuzinsky, M. Jacunski, C. Ransom, K. Settlemyer, L. Economikos, A. Simpson, A. Knorr, M. Naeem, G. Stojakovic, W. Robl, O. Gluschenkov, B. Liegl, C. Wu, Q. Wu, W.-K. Li, C.J. Choi, N. Arnold, T. Joseph, K. Varn, M. Weybright, K. McStay, W. Kang, Y. Li, S. Bukofsky, R. Jammy, R. Schutz, A. Gutmann, W. Bergner, R. Divakaruni, D. Back, E. Crabbé, W. Müller, G. Bronner","doi":"10.1109/VLSIT.2002.1015384","DOIUrl":null,"url":null,"abstract":"This paper describes a 110 nm half-pitch DRAM technology utilizing an 8F/sup 2/ vertical transistor trench cell and optimized for ease of manufacturing and scaling. All four critical lithography steps are regular patterns in the array. High performance is provided through the use of tungsten word-lines, tungsten bit-lines, and the double-gated vertical array transistors. Area enhancement techniques in the trench capacitor allow the use of conventional dielectric materials into the 110 nm generation. A 512 Mb prototype chip has been fabricated using this technology.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2002.1015384","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper describes a 110 nm half-pitch DRAM technology utilizing an 8F/sup 2/ vertical transistor trench cell and optimized for ease of manufacturing and scaling. All four critical lithography steps are regular patterns in the array. High performance is provided through the use of tungsten word-lines, tungsten bit-lines, and the double-gated vertical array transistors. Area enhancement techniques in the trench capacitor allow the use of conventional dielectric materials into the 110 nm generation. A 512 Mb prototype chip has been fabricated using this technology.
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