Uneven Current Mitigation in Single IGBT Chip with Multiple Metallization Regions Using Staggered Bonding Wires Layout

Abstract

The IGBT chip with large area and multiple metallization regions is popular in applications with large capacity. However, uneven current among metallization regions due to asymmetrical common inductance limits the expected capacity. Hence, this paper proposes a novel model to describe the uneven dynamic current among metallization regions and introduces the influence of switching speed, parasitic inductance and chip transconductance. Based on the analytical model, a staggered bonding wires layout is proposed to suppress the uneven current and semiconductor-circuit coupling simulations established by Sentaurus TCAD are carried out to verify the validity of the proposed method finally.