Enhanced performance of vertical double gate MOSFET (VDGM) with oblique rotating implantation (ORI) method

I. Saad, M. Riyadi, Zul Atfyi F. M. N., A. Hamid, R. Ismail
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引用次数: 3

Abstract

An enhanced performance of vertical double gate MOSFET (VDGM) structure was revealed by adopting the oblique rotating ion implantation (ORI) method. The device structure was simulated based on TCAD tools and verified by good matching data with the published experimental results. With ORI method a symmetrical self-aligned source/drain regions over the silicon pillar and sharp vertical channel profile was observed. With Lg = 50nm, the VT is 0.96V in double gate and increased to 1.2V in single gate structure. The sub threshold swing, S = 81.9 mV/dec and S = 87.7 mV/dec were obtained for double and single gate devices respectively. Similarly, large IDsat = 370µA/µm was observed for double gate compared to single gate device. By scaling the Lg into 50nm, the VT remains almost the same when the Lg is larger than 80nm. However, it decreases rapidly when scaled down to 50nm. The leakage current increases rapidly when the Lg is scaled down to 100nm and beyond. However, the ratio of ION – IOFF is seen to be increases even with shorter Lg. These results indicates that ORI method is essential for overcoming various SCE as scaling the channel length down to nanometer regime.
斜旋转注入法提高垂直双栅MOSFET (VDGM)性能
采用倾斜旋转离子注入(ORI)的方法增强了垂直双栅MOSFET (VDGM)结构的性能。基于TCAD工具对器件结构进行了仿真,结果与已发表的实验结果吻合良好。用ORI方法观察到硅柱上对称的自对准源/漏区和尖锐的垂直沟道轮廓。当Lg = 50nm时,双栅结构VT为0.96V,单栅结构VT增加到1.2V。双栅极和单栅极器件的亚阈值摆幅分别为S = 81.9 mV/dec和S = 87.7 mV/dec。同样,与单栅极器件相比,双栅极器件的IDsat = 370µA/µm。通过将Lg缩放到50nm,当Lg大于80nm时,VT几乎保持不变。然而,当缩小到50nm时,它迅速下降。当Lg缩小到100nm及以上时,泄漏电流迅速增加。然而,即使Lg越短,离子- IOFF的比率也越高。这些结果表明,ORI方法对于克服各种SCE是必不可少的,可以将通道长度缩小到纳米级。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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