Technology scaling and low-power data converter design

Abstract

The decrease of the supply voltage reduces the voltage headroom in analog circuits, the gate leakage current increases, the voltage gain decreases in planar bulk MOS transistors, 1/f noise deteriorate when using new high-k gate dielectrics. The consequences of the above limits are twofold: to remain a little behind the technology front and to push the analog digital interface toward the digital domain. However, a global digital world is impossible because signals of the real world are analog. Therefore, the trend is to focus on the interfaces: A/D and D/A, and minimize the analog preprocessing. Nevertheless, for achieving a suitable resolution it is necessary to design op-amps or OTA with an acceptable gain, and to obtain comparators with good sensitivity and low offset, thus facing in addition to the above the problem of correcting or compensating for the transistor and passive components mismatches.