Investigation in FIR filter to improve power efficiency and delay reduction

Abstract

In design of Finite Impulse Response (FIR) filter using adder, coefficients and multiplication are used. Multiple Constant Multiplication (MCM) is the algorithm which is used in FIR designing to minimize complexity of the circuit, increased delay and multiplication using large area. These problems can be optimized by using new technique known as digit-serial multiple constant multiplications. It reduces the complexity, delay and area utilization. Along with this already existed method, the modified carry select adder implemented in the current paper. It shows that there should be 10-20% increment in power efficiency and 50% reduction in delay compared to already exist techniques.