Heuristic Search based Test Pattern Compression Scheme

Abstract

VLSI testing becomes a mandatory process with invention of system-on chip to ensure device reliability. To assure the effectiveness of system-on chip, larger test data volume are required. This leads to excessive power consumption and also increases the device testing time. Additionally, larger memory is required to store this enormous test data. Hence, to overcome these drawbacks test data volume has to be reduced. This paper proposes a test data compression scheme based on Genetic algorithm to minimize test power. Test power minimization is accomplished by reducing hamming distance among test patterns. Proposed algorithm is implemented in c17 ISCAS’85 benchmark combinational circuit. Experimental result shows that 67.74% reduction on test pattern count and 49.35% reduction in hamming distance is observed.