Accelerating the Shuffled Frog Leaping algorithm by parallel implementations in FPGAs

Daniel M. Muñoz Arboleda, C. Llanos, L. Coelho, M. Ayala-Rincón
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Abstract

Meta-heuristics are efficient techniques for solving large scale optimization problems in which traditional mathematical techniques are impractical or provide suboptimal solutions. The Shuffled Frog Leaping algorithm (SFLA) is a stochastic iterative method, bio-inspired on the memetic evolution of a group of frogs when seeking for food, which combines the social behavior-based of the particle swarm optimization technique (PSO) and the global information exchange of memetic algorithms. However, the SFLA algorithm suffers on large execution times, being this problem clearly evident when solving complex optimization problems for embedded applications. This drawback can be overcome by exploiting the parallel capabilities of the SFLA. This paper proposes a hardware parallel implementation of the SFLA algorithm (HPSFLA) using FPGAs (Field Programmable gate Arrays) and the efficient floating-point arithmetic. The proposed architecture allows the SFLA to improve the functionality of the algorithm as well as to decrease the execution times by implementing parallel frogs and parallel memeplexes. Three well-known benchmark problems have been used to validate the implemented algorithm and simulation results demonstrate that the HPSFLA speeds-up by factors of 362, 727 and 211 a C-code implementation using an embedded microprocessor for the Sphere, Rastrigin and Rosenbrock benchmarks problems, respectively. Synthesis, simulation and execution time results demonstrate the effectiveness of the proposed HPSFLA architecture for embedded optimization systems.
用fpga并行实现加速洗牌青蛙跳跃算法
元启发式是解决大规模优化问题的有效技术,在这些问题中,传统的数学方法是不切实际的或提供次优解。shuffle Frog hopping algorithm (SFLA)是一种随机迭代算法,以青蛙群体觅食过程中的模因进化为灵感,将基于社会行为的粒子群优化技术(PSO)与模因算法的全局信息交换相结合。然而,SFLA算法的执行时间很长,在解决嵌入式应用程序的复杂优化问题时,这个问题非常明显。这个缺点可以通过利用SFLA的并行能力来克服。本文提出了一种利用fpga(现场可编程门阵列)和高效浮点算法实现SFLA算法(HPSFLA)的硬件并行实现。所提出的体系结构允许SFLA改进算法的功能,并通过实现并行青蛙和并行memeplexes来减少执行时间。利用三个著名的基准测试问题验证了所实现的算法,仿真结果表明,采用嵌入式微处理器的c代码实现的HPSFLA在Sphere、Rastrigin和Rosenbrock基准测试问题上的速度分别提高了362倍、727倍和211倍。综合、仿真和执行时间的结果证明了所提出的HPSFLA架构在嵌入式优化系统中的有效性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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