A Multiway Partitioning Algorithm for Parallel Gate Level Verilog Simulation

Abstract

We describe, in this paper, a multiway partitioning algorithm for parallel gate level Verilog simulation. The algorithm is an extension of a multi-level algorithm which only creates two partitions. Like its predecessor, it takes advantage of the design hierarchy present in a Verilog circuit design. The information it makes use of is contained in the modules and their instances. The algorithm makes use of a hypergraph model of the Verilog design in which a vertex in the hypergraph represents a module instance. Our new algorithm relies upon a metric whose function is to balance the load and the communications between the modules of the Verilog design. pre-simulation is used to to evaluate the partitioning metric. When compared to hMetis, a well known multilevel partitioning algorithm, our algorithm produces a superior speedup and a reduced cut-size.