A Linear Mode CMOS Power Amplifier with Self-Linearizing Bias

Abstract

A biasing scheme that improves the linearity of linear mode power amplifiers (PA) is presented. This technique employs adding feedback to a current mirror bias to enhance the linearity of the amplifier by compensating the nonlinear input capacitance of the core transistor. The technique is verified with simulations and implemented in a prototype 2.4 GHz PA for WLAN application. The PA is fabricated in a 0.35-mum CMOS and achieves a small-signal gain of 25.4 dB, output P1dB of 25.1 dBm, and a power-added efficiency (PAE) of 40%.