Design and Analysis of Memristor-CMOS Based Hybrid D Latch

Abstract

The discovery of the memristor, also known as the fourth missing element after resistor, inductor and capacitor, has shown emerging growth in nanoscale devices. The properties of non-volatility, small size and low power will be a significant advantage in the upcoming generation of chip design. Flip-Flops are sequential circuits with applications like registers, counters, frequency dividers etc. They can be generated by cascading latch in a master-slave configuration. This paper proposes a design of a D latch cascaded in master-slave configuration for designing a D flip-flop. This paper also compares various methods for designing D latch using the memristor-CMOS hybrid technique and Memristor ratioed logic (MRL). All the simulations were performed on Cadence Virtuoso, VTEAM model for memristor and CMOS 90nm technological file were used.