168 Gb/s line rate real-time PAM receiver enabled by timing recovery with 8/7 oversampling in a single FPGA

Abstract

Demonstration of a real-time receiver working with 28 GBd at 32 GSa/s. The signal processing is done on a single FPGA. The resource-saving non-integer oversampling of 8/7 is enabled by a timing synchronization in the frequency domain.