Bit synchronizer performance in the presence of signal transition variation

Abstract

The author addresses the effect on the performance of the DTTL (data transition tracking loop) symbol synchronizer of the signal transition variation due to signal transition density, data asymmetry, and sinusoidal modulation. It is shown that the combination of these factors will indeed affect the DTTL performance, e.g. clock jitter and cycle slippage rate, and that worst-case performance may result if the parameters are not well selected. Typical numerical results are shown.<>