CMOS circuit realization of a truncated Viterbi decoder using pipeline technique

Abstract

Data coding transfer is one of the major problem encountered in many digital communication systems. The main disadvantage of the Viterbi decoder circuit implemented so far is the huge memory size required to store all the path. A novel design of the proposed Viterbi decoder using CMOS digital circuits is illustrated. It has several advantages over the previous implementations. It is based on a pipeline architecture which results in parallel processing leading to very high speed. Furthermore, it uses the truncated Viterbi algorithm which results in reducing the memory size and consequently the Si area required to be integrated.