Electrical Noise Analysis of an Integrated Patch-Clamp Amplifier

Abstract

This paper presents an evaluation of electrical noise sources and signal-to-noise limitations in a fabricated integrated patch-clamp amplifier. We also present numerical calculation of the theoretical noise of the patch-clamp system. Our fabricated device was measured to have less than 4pA of rms noise at 10 kHz bandwidth, similar in performance to commercial bench- top systems. The integrated patch-clamp can accurately measure nano-Amperes of current and is intended for a high-throughput system that can screen a large number of cells in parallel. The fabricated device consumes 1480 by 1300 mum of silicon area and 3.2 mW at 3.3 V of power. The device was fabricated using AMI 0.5 mA Micron technology.