Experimental investigation of high voltage and high current gain of a lateral bipolar transistor based on a lateral DMOS structure

Abstract

Experimental results of a lateral high voltage NPN transistor based on a lateral DMOS structure fabricated in a low cost power BiCMOS technology are presented. Common-emitter current gain of typical devices were about 300 for the lateral devices compared to about 100 for a vertical device. The lateral NPN devices had emitter to collector breakdown voltages of 30 and 70 volts depending on the length of the collector region.