Considering multi-cycle influences for signal selection for Post Silicon Validation

Abstract

Post-silicon validation is an important step in the chip design life cycle. This involves observing the signal elements of the chip to check if the signals have the expected values. The process essentially requires observing the circuit behaviour (i.e. the signal values) on giving known inputs, and checking for correctness and conformance. The size of the trace buffer which stores the values of the signals during the post-silicon validation step, limits the number of signals that can be observed. Deciding the best signal set to monitor given the constraint on the size of the trace buffer is an important task. In this paper, we present an algorithm for signal selection, that allows us to select signals which, on traced, gives us better restoration than existing techniques.