A 125mV 2ns-access-time 16Kb SRAM design based on a 6T hybrid TFET-FinFET cell

Abstract

This paper proposes a robust and energy-efficient hybrid TFET-FinFET 6T SRAM cell which takes advantage of the higher ON/OFF current ratio of TFETs compared to that of FinFETs to reliably hold and access data at ultra-low supply voltages. More precisely, in the proposed hybrid cell, to achieve low static currents along with high noise margins, TFETs are used for cross-coupled inverters, and to speed up the access time, high-performance FinFETs are utilized for access transistors. The paper also presents a dual-Vt 6T SRAM, in which low-power (high-Vt) and high-performance (low-Vt) FinFETs are used for cross-coupled inverters and access transistors, respectively. For both SRAM cells, the Vdd boost read-assist technique is employed to improve the read stability. Characteristics of both SRAMs are analyzed using HSPICE simulations for technologies with the gate length of 20 nm for a 128\times 128 SRAM array. Simulation results reveal that the lowest operating Vdd for the dual-Vt cell is 225 mV, whereas that of the hybrid cell is 125 mV. Moreover, to further decrease the access delay of the hybrid cell for 125 mV ≤ Vdd ≤ 225 mV, negative Gnd read-assist technique and a boosted voltage for the row decoder are used. Finally, the paper presents a 125mV 2ns-access-time 16Kb SRAM array based on the proposed hybrid TFET-FinFET SRAM cell.