High-linearity zero-voltage switching current memory cell for measurement applications

Abstract

In this paper, a high-linearity version of the zero voltage switching (ZVS) current memory cell is presented. The linearity improvement is achieved by using a high-linear differential pair and compensation switch. Higher power efficiency is also obtained by utilizing a Recycling Folded Cascode (RFC). The proposed memory cell is implemented using CMOS 0.35μm and Cadence Spectre simulations are presented to validate the improvements. The proposed structure is used to implement an integrator which achieved a DC gain of 89.44 dB.