Systolic Array based Multiply Accumulation Unit for IoT Edge Accelerators

P. Lahari, S. Yellampalli, R. Vaddi
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引用次数: 1

Abstract

Accelerator is a hardware that runs along with the processor and executes the key functions much faster than the processor. The Main purpose of the Accelerator is to increase speed. Deep Neural Networks has achieved wide results in the various Machine Learning Applications Such as image, video, text classification and language translation. The purpose of DNN Accelerators is to speed up the most complex Computation i.e., matrix multiplication. Systolic array Based Accelerator seems like multiply Accumulate unit with Systolic Array based multiplication followed by Adder and accumulator. Multiply Accumulate Unit comprises multiplier, adder and Accumulator. Multiplier is designed used systolic array and that output is given as one of the inputs to the adder followed by Accumulator. In this paper general Matrix based Multiply Accumulate Unit is compared with systolic array based Multiply Accumulate Unit using Xilinx ISE 14.5, various parameters like area, delay and speed are compared. Systolic Array based Multiply Accumulate Unit consumes less area of 49%, less delay of 35% and in turn provides high speed when compared with general matrix multiplier-based multiplier Accumulate unit.
基于收缩阵列的物联网边缘加速器乘法积累单元
加速器是一种与处理器一起运行的硬件,它执行关键功能的速度比处理器快得多。加速器的主要目的是提高速度。深度神经网络在各种机器学习应用中取得了广泛的成果,如图像、视频、文本分类和语言翻译。DNN加速器的目的是加速最复杂的计算,即矩阵乘法。基于收缩数组的加速器看起来就像用基于收缩数组的乘法乘以累加器和累加器。乘法累加单元包括乘法器、加法器和累加器。乘法器是用收缩阵列设计的,输出作为加法器的一个输入,然后是累加器。本文利用Xilinx ISE 14.5对基于一般矩阵的乘法累加单元和基于收缩阵列的乘法累加单元进行了比较,比较了面积、延迟和速度等参数。与一般基于矩阵乘法器的乘法器累积单元相比,基于收缩阵列的乘法器累积单元消耗的面积少49%,延迟少35%,速度高。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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