Exploring High Efficiency Hardware Accelerator for the Key Algorithm of Square Kilometer Array Telescope Data Processing

Abstract

The SKA (Square Kilometer Array) radio telescope under construction will become the largest telescope in the world by integrating the sampled data from a huge number of small antenna nodes in the array to emulate a giant antenna. Due to the limited storage space, the SKA needs to process massive data in real-time, which makes the SKA scientific data processing become a bottleneck of the computational performance. However, existing off-the-shelf high performance computing solutions cannot meet the computation requirements (5 times more than top 1 supercomputer) as well as low power budget (1/3 of the power of the top 1 supercomputer). In this paper, we explore high efficiency solution design based on FPGA by addressing the most representative key algorithm in SKA data processing, i.e. Gridding, which is the most time and memory consuming. We propose an efficient hardware accelerator design of Gridding algorithm on FPGA, which would the first FPGA based design of Gridding algorithm in this community. In our design, we unfold the third loop in the Gridding algorithm and design corresponding hardware pipeline stages to achieve the high efficiency hardware acceleration. The functionality and performance of our design is verified in both simulation and FPGA prototyping board, whose results show that our proposed hardware implementation achieved great improvement in performance compared with software implementation running on generic CPUs. We believe our design would be a strong candidate design to solve the bottleneck in SKA data processing.