{"title":"A coherent ultra-wideband receiver IC system for WPAN application","authors":"Yan Tong, Yuanjin Zheng, Y. Xu","doi":"10.1109/ICU.2005.1569957","DOIUrl":null,"url":null,"abstract":"An integrated pulse based ultra-wideband (UWB) receiver using a coherent architecture is presented. BPSK modulation of monocycle Gaussian pulses which meet FCC's UWB frequency band (3.1 - 10.6 GHz) is adopted. The received pulses are correlated with template pulses from a local pulse generator. In each period the correlation value is either sampled by a high speed ADC for further signal processing or sent to a comparator to recover the transmitted data. Simulation and primary measurement results show that the receiver can achieve a demodulation rate of 100/220/480 Mbps and consumes 99 mW peak power. The design is based on a 0.18-/spl mu/m CMOS process.","PeriodicalId":105819,"journal":{"name":"2005 IEEE International Conference on Ultra-Wideband","volume":"75 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"31","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 IEEE International Conference on Ultra-Wideband","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICU.2005.1569957","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 31
Abstract
An integrated pulse based ultra-wideband (UWB) receiver using a coherent architecture is presented. BPSK modulation of monocycle Gaussian pulses which meet FCC's UWB frequency band (3.1 - 10.6 GHz) is adopted. The received pulses are correlated with template pulses from a local pulse generator. In each period the correlation value is either sampled by a high speed ADC for further signal processing or sent to a comparator to recover the transmitted data. Simulation and primary measurement results show that the receiver can achieve a demodulation rate of 100/220/480 Mbps and consumes 99 mW peak power. The design is based on a 0.18-/spl mu/m CMOS process.