Jae Ho Lee, P. Rogers, M. A. Carpenter, E. Eisenbraun, Yongqiang Xue, R. Geer
{"title":"Synthesis and Properties of Templated Si-based Nanowires for Electrical Transport","authors":"Jae Ho Lee, P. Rogers, M. A. Carpenter, E. Eisenbraun, Yongqiang Xue, R. Geer","doi":"10.1109/NANO.2008.173","DOIUrl":null,"url":null,"abstract":"Self-assembled Si nanowires (SiNWs) have been synthesized and characterized as a template for surface metal silicide formation to investigate electron transport at the nanowire surface. Silicon nanowires were directly grown on silicon substrates via the solid-liquid-solid (SLS) growth process. Preliminary synthesis utilized high-temperature processing of a sputtered Au catalyst film on Si (100) and (111) substrates in an oxygen-filtered Ar ambient. SiNW diameter was a roughly monotonic function of the growth time/temperature. The diameters of the SiNW templates ranged from approximately 5 nm to 180 nm. Ni deposition on the SLS SiNWs and post-deposition thermal processing was carried out for silicide formation. Metal-silicide coated nanowires were dispensed on metal-patterned Si wafers for electrical characterization and exhibited an improvement in conductivity of several orders of magnitude.","PeriodicalId":150729,"journal":{"name":"2008 8th IEEE Conference on Nanotechnology","volume":"120 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 8th IEEE Conference on Nanotechnology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NANO.2008.173","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
Self-assembled Si nanowires (SiNWs) have been synthesized and characterized as a template for surface metal silicide formation to investigate electron transport at the nanowire surface. Silicon nanowires were directly grown on silicon substrates via the solid-liquid-solid (SLS) growth process. Preliminary synthesis utilized high-temperature processing of a sputtered Au catalyst film on Si (100) and (111) substrates in an oxygen-filtered Ar ambient. SiNW diameter was a roughly monotonic function of the growth time/temperature. The diameters of the SiNW templates ranged from approximately 5 nm to 180 nm. Ni deposition on the SLS SiNWs and post-deposition thermal processing was carried out for silicide formation. Metal-silicide coated nanowires were dispensed on metal-patterned Si wafers for electrical characterization and exhibited an improvement in conductivity of several orders of magnitude.