Techniques for optimizing statistical simulations (IC processes)

Abstract

The authors address the methodology developed for the Florida SEMATECH Center of Excellence (FSCOE) for performing statistical simulations of integrated circuit processes. This methodology involves doing a series of statistical simulations at the process, device, and circuit design levels. Various techniques to improve the amount of time it takes to obtain results from statistical simulations of processes using Suprem-IV are described. Methods the design engineer can use, rather than means of improving the models in the simulator are considered. The key to this methodology is that multiple simulations are performed in order to obtained the statistical results to adequately model the effect of the variation in the fab. Five possible techniques are outlined that reduce the simulation time and eliminate the need to buy expensive computer equipment or use less accurate simulation models.<>