Gate-first high-k/metal gate stack for advanced CMOS technology

Y. Nara, N. Mise, M. Kadoshima, T. Morooka, S. Kamiyama, T. Matsuki, M. Sato, T. Ono, T. Aoyama, T. Eimori, Y. Ohji
{"title":"Gate-first high-k/metal gate stack for advanced CMOS technology","authors":"Y. Nara, N. Mise, M. Kadoshima, T. Morooka, S. Kamiyama, T. Matsuki, M. Sato, T. Ono, T. Aoyama, T. Eimori, Y. Ohji","doi":"10.1109/ICSICT.2008.4734777","DOIUrl":null,"url":null,"abstract":"Practical and manufacturable solutions for metal gate/dual high-k CMOS integration are presented. In order to overcome the difficulties of threshold voltage control of metal gate/high-k gate stack especially for gate-first integration, several material designs have been proposed so far. These include different metal gate materials and different high-k materials which are separately used in nMOS and pMOS transistors. These approaches sometimes bring about complicated CMOS integration scheme. In this paper, therefore, we will give simple metal gate/dual high-k CMOS fabrication processes with low threshold voltages which are suitable for scaled CMOS device manufacturing.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"110 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSICT.2008.4734777","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

Abstract

Practical and manufacturable solutions for metal gate/dual high-k CMOS integration are presented. In order to overcome the difficulties of threshold voltage control of metal gate/high-k gate stack especially for gate-first integration, several material designs have been proposed so far. These include different metal gate materials and different high-k materials which are separately used in nMOS and pMOS transistors. These approaches sometimes bring about complicated CMOS integration scheme. In this paper, therefore, we will give simple metal gate/dual high-k CMOS fabrication processes with low threshold voltages which are suitable for scaled CMOS device manufacturing.
用于先进CMOS技术的栅极优先高k/金属栅极堆栈
提出了金属栅/双高k CMOS集成的实用和可制造的解决方案。为了克服金属栅极/高k栅极堆叠的阈值电压控制困难,特别是栅极优先集成,目前已经提出了几种材料设计。这些包括不同的金属栅极材料和不同的高k材料,分别用于nMOS和pMOS晶体管。这些方法有时会带来复杂的CMOS集成方案。因此,在本文中,我们将给出简单的金属栅极/双高k CMOS制造工艺,具有低阈值电压,适用于规模化CMOS器件制造。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信