A Distortion-Free VCO-Based Sensor-to-Digital Front-End Achieving 178.9dB FoM and 128dB SFDR with a Calibration-Free Differential Pulse-Code Modulation Technique

Jiannan Huang, P. Mercier
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引用次数: 10

Abstract

Motion and stimulation artifacts encountered in wearable sensors present difficult dynamic range (DR) and linearity challenges: AFEs need to be able to resolve $\mu \mathrm{V} -$ level signals in the presence of artifacts up to 100s of mV in amplitude while maintaining linearity without saturation, such that the signal of interest can be readily recovered during post-processing. Since it is not possible to build an amplifier with appreciable gain and linearity for $ \gt 100$ mV inputs under $ \lt 1\mathrm{V}$ SoC-compatible supply, most high-DR AFEs instead incorporate an LNA into $\mathrm{a}\Delta \sum -$ based ADC-direct architecture [1] –[3]. However, as many emerging wearable devices desire single-chip integration in scaled CMOS for size and digital performance considerations, conventional $\Delta \sum$ Ms, which rely on voltage-domain building blocks, suffer from reduced intrinsic gain and headroom. Instead, time-domain quantization through VCO-based AFEs benefits from scaled CMOS and offers intrinsic $1 ^{st} -$ order noise shaping. However, the non-linear V-F conversion of conventional VCO-based AFEs makes achieving a large and linear DR difficult [1]. To address this, [3] adopts a differential pulse code modulation (DPCM) technique that enables the VCO to process only a small prediction error, VERR, by subtracting from $V_{IN}\mathrm{a}$ digital predictor value fed through a DAC (Fig. 28.1.1 top). Maximal linearity would be achieved if the predictor was perfect, resulting in $V_{ERR},\approx 0$; however, this requires a highperformance and power-expensive DAC. Therefore, [3] truncates the predictor’s output, reducing the DAC requirements to 9b, but adding truncation error, ET. If the gain of paths P1 and P2 are made equal, which is enforced in [3] via a gain error calibration (GEC) circuit, ET will ideally cancel at the output. However, it is not possible to achieve perfect ET cancellation, and any residual ET will degrade SQNR, limiting the extent to which truncation can be used to relax the DAC’s resolution. In addition, GEC itself introduces power overhead.
基于无失真vco的传感器-数字前端,采用免校准差分脉冲编码调制技术实现178.9dB FoM和128dB SFDR
在可穿戴传感器中遇到的运动和刺激伪影存在困难的动态范围(DR)和线性挑战:AFEs需要能够在伪影存在的情况下解析$\mu \mathrm{V} -$电平信号,同时保持无饱和的线性,以便在后处理过程中很容易恢复感兴趣的信号。由于不可能在$ \lt 1\mathrm{V}$ soc兼容电源下为$ \gt 100$ mV输入构建具有可观增益和线性度的放大器,因此大多数高dr afe将LNA纳入基于$\mathrm{a}\Delta \sum -$的ADC-direct架构[1]-[3]。然而,由于许多新兴的可穿戴设备出于尺寸和数字性能的考虑,希望将单芯片集成到缩放的CMOS中,传统的$\Delta \sum$ m依赖于电压域构建模块,因此固有增益和净空空间降低。相反,通过基于vco的afe进行时域量化受益于缩放CMOS,并提供固有的$1 ^{st} -$阶噪声整形。然而,传统的基于vco的AFEs的非线性V-F转换使得实现大的线性DR变得困难[1]。为了解决这个问题,[3]采用差分脉冲编码调制(DPCM)技术,通过减去通过DAC馈送的$V_{IN}\mathrm{a}$数字预测值(图28.1.1顶部),使VCO仅处理很小的预测误差VERR。如果预测器是完美的,将实现最大的线性,结果为$V_{ERR},\approx 0$;然而,这需要高性能且功耗昂贵的DAC。因此,[3]截断了预测器的输出,将DAC要求降低到9b,但增加了截断误差ET。如果路径P1和P2的增益相等,这在[3]中通过增益误差校准(GEC)电路强制执行,ET将在输出处理想地抵消。然而,不可能实现完美的ET抵消,任何残留的ET都会降低SQNR,限制了截断可以用来放松DAC分辨率的程度。此外,GEC本身还引入了功率开销。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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