Analysis and Modeling of Hybrid Analog-digital PLL

Abstract

A hybrid analog-digital phase-locked loop (PLL) takes the advantage of flexibility and precision, and is inherently suited for integration with digital systems because of the digital interfaces in its structure. The hybrid analog-digital PLL studied in this paper consists of an analog phase detector (PD), an analog low noise amplifier (LNA), an analog-to-digital converter (ADC), a digital loop filter, a digital controlled oscillator, and a frequency measurement module. The hybrid structure makes it difficult to model the phase noise characteristics of this type of hybrid PLL, to overcome this problem, the method of equivalent a discrete section to a continuous one was used. And the linear frequency domain model of the hybrid analog-digital PLL was presented. In this model, the contribution of each noise source to the total phase noise can be calculated, once the phase noise property of each main noise source is obtained. Validation of this model was performed by comparing the numerical simulation results and the measurements on the prototype. The experiment results showed that the phase noise predicted by the model agrees with that of the measured in our prototype. The potential application of the model proposed in this paper is to be used to design a hybrid analog-digital PLL with promising phase noise performance.