Ensuring On-Die Power Supply Robustness in High-Performance Designs

Abstract

VLSI designs in advanced technology nodes increasingly have more power dissipation packed in a smaller area due to high levels of logic integration. Local power demand causes high current to flow through a power distribution network which is normally designed based on average current considerations, while even in normal switching scenarios, the average current is much less than the peak current. The instantaneous flow of high current results in dynamic voltage drops in the power network, which can affect the design performance. In this paper, we discuss methods to ensure power grid robustness by avoiding high dynamic voltage drop issues, and hence improve the overall reliability of the design. The analyses and techniques were adopted on a ~100 sq.mm., 40nm system-on-chip (SoC) design with peak clock frequency of 1.2GHz, and having 10 individual processors along with a collection of hardware accelerators. We also present relevant results highlighting the overall improvements seen.