{"title":"Extending C/ID Methodology for Optimal Implementation of Single-Stage Discrete-Time Amplifiers","authors":"Sakthidasan Kalidasan, A. Tajalli","doi":"10.1109/SMACD58065.2023.10192114","DOIUrl":null,"url":null,"abstract":"A flow to develop single-stage Discrete-Time (DT) amplifiers based on a set of given requirements, including speed and noise specifications, will be introduced. To reduce the computational complexity of the proposed design flow, C/ID methodology has been employed as the baseline. To demonstrate effectiveness of the proposed design flow, a DT amplifier will be developed to satisfy target performance parameters, namely speed, voltage gain, and noise, when consumption is minimized. The performance of the resulted design shows less than 3% error with respect to the target values. Low complexity of the flow, together with high achievable precision, makes the proposed approach a very appropriate choice for developing analog Electronic Design Automation (EDA) tools.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMACD58065.2023.10192114","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A flow to develop single-stage Discrete-Time (DT) amplifiers based on a set of given requirements, including speed and noise specifications, will be introduced. To reduce the computational complexity of the proposed design flow, C/ID methodology has been employed as the baseline. To demonstrate effectiveness of the proposed design flow, a DT amplifier will be developed to satisfy target performance parameters, namely speed, voltage gain, and noise, when consumption is minimized. The performance of the resulted design shows less than 3% error with respect to the target values. Low complexity of the flow, together with high achievable precision, makes the proposed approach a very appropriate choice for developing analog Electronic Design Automation (EDA) tools.