Efficient parallel algorithms for search problems: applications in VLSI CAD

Abstract

Experimental results are presented to demonstrate that it is possible to speed up search-based algorithms by several orders of magnitude. Highly optimized sequential programs were first implemented in the C language for two applications: floor plan verification and tautology verification. Then parallel programs were developed for the Ncube by modifying the sequential programs to incorporate dynamic load balancing. The speedups obtained on 1024 processors ranged from 430 to 1099 for floor plan optimization, with larger problems showing higher speedups. For tautology verification the speedup on 1024 processors ranged from 564 to 1007, with larger problems again showing higher speedups.<>