Simulation and Experimental Research of the Enhanced BPSK and QPSK Demodulator

Abstract

This paper considers a method of improvement the noise immunity of the phase-locked loops (PLL), which are an integral part of modern radio receivers and ensure the operability of these receivers. The methods of the research were simulation and full-scale experiments. The results of the simulation show the possibility of reducing the noise threshold of the PLL by 1.5-2 dB in case when input signal is a mixture of noise and digital radio signals with modern types of modulation. For the full-scale experiment the authors used the binary and quadrature phase-shift keying (BPSK, QPSK) signal generator (developed on DDS technology) on the PSoC 4 platform, as well as a demodulator based on an enhanced PLL, developed on the Xilinx field-programmable gate array (FPGA) platform. The results of experiments demonstrate an adequacy of simulation models and the possibility of the noise immunity improvement.