Area efficient, high-speed VLSI design for EBCOT block coder in JPEG 2000

Abstract

With the growth in multimedia technology, demand for highspeed real time image compression system has also increased. JPEG 2000 standard is developed to cater such application requirements. However, the sequential execution of the bit plane coder (BPC) used in this standard consumes more clock cycles. To improve the performance of the BPC, a new concurrent context modeling technique is proposed in this paper. To study number of context generated in each clock cycle, analysis is carried out on five ISO grayscale images with size 512 × 512. The study revealed that about 58% of time more than 4 contexts are generated in one clock. Therefore, a new concurrent context coding architecture is proposed in this paper. It is implemented on Startix FPGA and the hardware requirement is reduced significantly, compared to similar architectures. Moreover, number of clock cycles required to encode a bit plane is reduced by 10% and it is minimum 2.5 times faster than the similar designs in existence. This design operates at 164.47 MHz, which makes it compatible for encoding HDTV 1920 × 1080 4:2:2 at 39 frames per second.